In fabricating Damascene and Dual Damascene (DD) copper interconnects in accordance with prior art techniques, copper is encased in one or more copper diffusion barrier layers. Typically, the bilayer Ta/TaNX is used as a barrier layer for sidewalls and at the bottom of lines, and a relatively high-k dielectric layer, typically silicon nitride (or silicon carbide, or silicon carbide nitride, or silicon oxide carbide nitride), is used as a top capping barrier layer.
Sites of poor adhesion between copper and metallic barrier layers on sidewalls and/or at the bottom of openings may result in electromigration (EM) and/or Stress Induced Voids (SIV). Copper EM and SIV are important reasons for poor reliability and low yields in copper interconnects. Presently used sidewalls and bottom barrier layers, such as Ta, TaNX, Ta/TaNX, Ru, TaSiXNY, WNX, Ti/TiNX, TiSiXNY, or WSiXNY, are problematic because: (a) their relatively high resistivity increases the resistance of interconnect lines and vias—this is particularly problematic at the bottom of vias; (b) they may have poor adhesion to copper and/or to the dielectric surrounding the interconnect (inter layer dielectric or ILD), resulting in high EM and/or SIV; and (c) they are often discontinuously deposited by a PVD technique over sidewalls of high aspect ratio (HAR) Damascene and Dual Damascene vias and trenches (particularly on hard to reach lower sidewalls of HAR openings, and on negative slope vicinities of undercut crevices, nooks, and crannies)—which discontinuities provide easy diffusion routes for copper into surrounding dielectric and/or copper voids.
In light of the above, there is a need for methods and materials that solve one or more of the above-identified problems.